Planar semiconductor device

ABSTRACT

In a semiconductor chip with a planar structure, the width of each corner portion of a peripheral electrode in a diagonal direction of the chip is made almost the same as the width of each straight portion of the peripheral electrode, the peripheral electrode having the same potential as a drain electrode in the periphery of the chip. The corner portion of the peripheral electrode is in the form of a partial annular ring. Degradation of the withstand voltage in the semiconductor device is prevented in the high-temperature and high-humidity conditions.

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT

The present invention relates to a planar semiconductor device with aplanar structure having an annular metallic film in a peripheral area ofa chip, which is applicable to a MOSFET, an insulated gate bipolartransistor, a MOS gate thyristor and the like.

FIG. 3 is a perspective view of a resin-molded semiconductor devicesealed with a resin. A semiconductor chip 21 is joined to a lead frame22 and is sealed with a resin 23. Reference numeral 24 designates a wireconnecting the lead frame 22 to the semiconductor chip 21.

FIG. 4 is a partial plan view of a corner portion of a vertical MOSFETchip, which is an example of a planar semiconductor device. A sourceelectrode 2 constituting a cell portion through which a current isconducted, a withstand voltage structure section 3 with a field platestructure, and a peripheral electrode 4 are seen through a passivationfilm 1 covering almost the entire surface of the chip. Generally, theperipheral electrode 4 has the same potential as a drain electrode onthe reverse surface.

FIG. 5 is a partial sectional view taken along line 5—5 in FIG. 4. Theleft side of this view is a peripheral portion, the right side is thecell portion, and an intermediate withstand voltage structure isomitted. First, the cell portion is described. A p base region 6 isselectively formed on a surface layer of an n drift layer 5 with highresistivity. An n⁺ source region 7 is formed inside the p base region 6,and the source electrode 2 is formed in contact with surfaces of boththe p base region 6 and the n⁺ source region 7. A gate electrode 9 isprovided, via a gate oxide film 8, on the surface of the p base region 6sandwiched by an exposed surface portion of the n drift layer 5 and then⁺ source region 7. Reference numeral 10 designates an interlayerinsulation film for insulating the gate electrode 9 and the sourceelectrode 2. Reference numeral 1 denotes a passivation film.

In the peripheral portion of the chip, a p⁺ peripheral region 12 isformed on a surface layer of the n drift layer 5, the peripheralelectrode 4 is formed in contact with a surface of the p⁺ peripheralregion 12, and the passivation film 1 covers the peripheral electrode 4.The peripheral electrode 4 has a potential equal to that of a drainelectrode (not shown) and is extended over a thick field oxide film 13constituting the withstand voltage structure section to form a channelstopper. The peripheral electrode 4 and the source electrode 1 aretypically comprised of an aluminum alloy containing silicon.

The corner portion of a rectangular MOSFET chip, particularly an insideof the corner portion, is normally shaped to have a curvature (thisshape is hereafter referred to as a “curved shape”) instead of a patternwith an acute angle, in order to weaken the electric field in the chipif a voltage is applied in an off-condition.

In the corner portion in FIG. 4, the outer end of the source electrode2, the inside of the withstand voltage structure section 3 and theperipheral electrode 4 are formed into curved shapes, that is,quarter-circular arcs.

The outside of the outer end of the peripheral electrode 4, however, isoften formed to have an almost right-angle corner instead of a curvedshape in order to maintain contact with the peripheral region 12 and tostably apply a voltage to the drain electrode. Thus, the width of thecorner portion of the peripheral electrode 4 is about three times largerthan that of the straight portion.

The results on high-temperature and high-humidity reliability tests onsuch chips, however, indicate that in some chips, the withstand voltagecharacteristic becomes degraded. When such a degraded chip is examined,cracks are found in the passivation film 1 of the element, and many ofthem are present in the outer peripheral portions and corner portions ofthe chip.

This is because stress is concentrated on the outer peripheral portionsand corner portions of the chip and because the cracks are developed asa result of thermal stress originating from a heat cycle or a powercycle. In particular, for a molded element comprising a chip sealed witha resin, stress concentration is severe due to an additional residualstress in the resin. Another reason is a large difference in thermalexpansion coefficient between the aluminum alloy constituting theperipheral electrode and silicon nitride constituting the passivationfilm.

When such a semiconductor device is placed in a high-temperature andhigh-humidity environment, the atmosphere around the chip or moisture inthe resin enters through the cracks into the passivation film. On theother hand, the cracks may develop and cause the passivation film topeel off, thereby exposing an aluminum electrode in the underlayer,which reacts with moisture in the atmosphere. The aluminum alloyelectrode corrodes due to local battery action or the like, degradingthe withstand voltage characteristic of the semiconductor device.

In view of this problem, it is an object of the present invention toprovide a reliable semiconductor device by preventing cracks,particularly in the portions of the passivation film located in the chipcorners.

SUMMARY OF THE INVENTION

To attain the object, the present invention provides a planarsemiconductor device having a metallic film in the form of a closed ringin a peripheral area of a square semiconductor chip. The metallic filmis covered with a passivation film. The width of a portion of themetallic film located in each corner portion of the chip in achip-diagonal direction is almost the same as the width of each straightportion of the metallic film.

The most common shape of the metallic film is, for example, a partialannular ring.

This configuration reduces the difference in thermal expansion betweenthe passivation film and the metallic film to prevent formation ofcracks in the chip corner portions.

In particular, in a semiconductor device sealed with a molding resin,stress concentration due to residual stress or the like in the moldingresin is likely to cause cracks. The above configuration, however,alleviates the stress concentration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial plan view of a vertical MOSFET according to anembodiment of the present invention;

FIG. 2 is a partial sectional view of the MOSFET taken along line 2—2 inFIG. 1;

FIG. 3 is a perspective view of a conventional resin-mold semiconductordevice;

FIG. 4 is a partial plan view of a conventional vertical MOSFET; and

FIG. 5 is a partial sectional view of the MOSFET taken along line 5—5 inFIG. 4.

DETAILED DESCRIPTION OF REFERRED EMBODIMENTS

FIG. 1 is a plan view of a corner portion of a vertical MOSFET chip,i.e. one embodiment of the present invention. A source electrode 2constituting a cell portion through which a current is conducted, awithstand voltage structure section 3 with a field plate structure, anda peripheral electrode 4 are seen through a passivation film 1 coveringalmost all the entire surface of the chip. The peripheral electrode 4has the same potential as a drain electrode (not shown).

This MOSFET differs from the conventional MOSFET in FIG. 3 in that theoutside of the peripheral electrode 4 has a curved shape to have almostthe same width as in the straight portion, i.e. partially circularannular shape.

FIG. 2 is a partial sectional view taken along line 2—2 in FIG. 1. Theleft part of this view is a peripheral portion, and the right part isthe cell portion through which a current is conducted. The intermediatewithstand voltage structure section is omitted. First, the cell portionis described. A p base region 6 is selectively formed on a surface layerof an n drift layer 5 with high resistivity. An n⁺ source region 7 isformed inside the p base region 6, and the source electrode 2 is formedto contact the surfaces of both p base region 6 and n⁺ source region 7.A gate electrode 9 of polycrystalline silicon is provided on the surfaceof the p base region 6, via a gate oxide film 8, which is sandwichedbetween an exposed surface portion of the n drift layer 5 and the n⁺source region 7. Reference numeral 10 designates an interlayerinsulation film, such as boron phosphorus silicate glass or the like,for insulating the gate electrode 9 and the source electrode 2.Reference numeral 1 denotes a passivation film of silicon nitride. Thesource electrode 2 is an aluminum alloy containing silicon.

In the peripheral portion of the chip, a p⁺ peripheral region 12 isformed on a surface layer of the n drift layer 5, and the peripheralelectrode 4 is formed in contact with a surface of the p⁺ peripheralregion 12. This structure, however, requires the peripheral electrode 4to contact only a silicon impurity diffusion layer in the p⁺ peripheralregion 12, and other portions of the p⁺ peripheral region 12 are coveredwith the passivation film 1. The peripheral electrode 4 has a potentialequal to that of a drain electrode and is extended over a thick fieldoxide film 13 to form a channel stopper, as in FIG. 4. Thus, the widthof the peripheral electrode 4 in a diagonal direction of the chip is 40μm, which is almost the same width as that of the straight portion, andabout a quarter of the conventional size.

In such a MOSFET, the occurrence rate of cracks in the passivation filmis reduced to about 10% of the conventional value or less. The resultsof long-time reliability tests in a high-temperature and high-humidityenvironment have shown that very few such MOSFETs suffer corrosion ofthe aluminum alloy or degradation of the voltage resistance, and thepercentage of defective chips has decreased substantially. This isbecause the above configuration alleviates the stress in the passivationfilm.

Although the above embodiment has been described in conjunction with theexample of a vertical semiconductor element with a peripheral electrodeat the same potential as the drain electrode, the present invention isnot limited to a vertical semiconductor element but may be a horizontaldevice or an integrated circuit.

As described above, according to the present invention, the width of theportion of the metallic film located in the corner portion of the squaresemiconductor chip in the chip-diagonal direction is almost the same asthat of the straight portion of the metallic film, thereby substantiallyreducing the possibility of defects caused by corrosion of the metallicelectrode or degradation of the withstand voltage that may occur underhigh humidity.

In particular, the present invention is effective in improving thereliability of general-purpose resin-semiconductor devices.

While the invention has been explained with reference to a specificembodiment of the invention, the explanation is illustrative and theinvention is limited only by the appended claims.

What is claimed is:
 1. A planar semiconductor device, comprising: asemiconductor chip having a square shape, and including a drift layerand a peripheral area formed on a surface layer of the drift layer, ametallic film having a closed ring shape formed on the peripheral areaof the semiconductor chip, said metallic film operating as a peripheralelectrode and including at least two straight portions and at least onecorner portion in a form of a partial annular ring between said at leasttwo straight portions, the width of the at least one corner portion ofthe metallic film located in a corner portion of the chip in achip-diagonal direction being substantially same as the widths of the atleast two straight portions of the metallic film so that the metallicfilm extends along an outer periphery of the chip with substantially thesame width, a passivation film covering the metallic film, and a moldingresin for sealing the semiconductor chip.
 2. A planar semiconductordevice according to claim 1, wherein said peripheral area includes a p⁺peripheral area having a silicon impurity diffusion layer, to which saidperipheral electrode only contacts, said passivation film covering aremaining area of said peripheral area.
 3. A planar semiconductor deviceaccording to claim 2, wherein said semiconductor chip includes awithstand voltage structure section extending along the outer peripheryof the chip with a curved corner, said metallic film with substantiallythe same width extending along the withstand voltage structure sectionwith the curved corner.